Data transmission device capable of feed-forward equalizing for transmission signals without delay circuits, and its operating method

Feed-Forward Equalizing Transmitter Without Delay Circuits Using D-Flip-Flops and Rotating Taps

This technology is a data transmission device where n D-flip-flops output transmitted data with a 1-bit parallel delay using distributed clocks of different phases generated by a clock distributor. n rotating taps then output these in a sequential, non-overlapping order, and a signal synthesizer combines them to create the final transmission signal. This structure implements Feed-Forward Equalizer (FFE) functionality without the need for separate delay circuits.

Since transmitted data becomes severely distorted while passing through a channel, FFEs that amplify and synthesize delayed data from pre, main, and post taps have been used. However, conventional FFEs required delay circuits to generate the delayed data. These delay circuits are sensitive to temperature and doping concentration, causing jitter, and the additional compensation circuits required to address this increase circuit area, complexity, and power consumption.

This technology generates time-delayed data directly using clock phase differences, eliminating the need for delay and compensation circuits, thereby reducing jitter and lowering circuit area and power consumption. Each rotating tap features a negative feedback linear regulator that supplies a fixed voltage, allowing the amplification level of each tap to be controlled via a control voltage. Applicable to high-speed SerDes, memory interfaces, and chip-to-chip wired data link transmitter ICs, it enables the design of smaller, lower-power transmitters while maintaining channel loss compensation performance.

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Key Features:

• A clock generator that outputs a clock signal of a preset frequency and a clock distributor that adjusts its phase to output n distributed clock signals of different phases
• n D-flip-flops that receive n-bit transmission data 1 bit at a time and output it with a delay based on the phase of the distributed clock signals
• n rotating taps that sequentially output the n-bit transmission data delayed by the D-flip-flops, 1 bit at a time, in a non-overlapping order
• n linear regulators that receive a control voltage to regulate the amplification level of each rotating tap and supply a fixed voltage to each tap via negative feedback

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This invention was developed with support from the Ministry of Education for the development of an Electrical Wireline Interface for 200G Ethernet.

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