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Parallel implementation method for a graphics processing unit executing edge-adaptive intra-field deinterlacing techniques

Listed on
2026-10-28
Edge-Adaptive Intra-Field Deinterlacing Accelerated via GPU Per-Pixel Thread Parallelization

This technology is a method for executing edge-adaptive intra-field deinterlacing in parallel on a graphics processing unit (GPU). It estimates a deinterlacing prediction model using six neighboring pixels around the target pixel based on geometric duality. By assigning one thread to each missing pixel, it interpolates a vast number of pixels simultaneously.

Interlaced broadcast formats like NTSC and PAL often suffer from flickering, artifacts, and field aliasing, while simple line-average interpolation tends to blur vertical edges. Although covariance-based adaptive deinterlacing preserves edge sharpness and provides superior image quality, its high computational demand—requiring a prediction model to be solved for every pixel—has historically limited real-time processing.

This technology distributes interlaced images and intermediate variables across multiple banks of GPU shared memory, allowing simultaneous thread access through block-level synchronization, while storing auto-generated variables in register memory to reduce access latency. It further minimizes transfer time by overlapping kernel operations and host transfers using asynchronous data streams and multi-GPU utilization. Applicable to digital TV receivers and broadcast video converters, it enables high-quality adaptive deinterlacing at real-time broadcast speeds.

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Key Features:
  • A step of estimating a deinterlacing prediction model using six neighboring pixels around a pixel to be interpolated based on geometric duality from an interlaced image
  • A parallel configuration where a graphics processing unit uses one thread to calculate each missing pixel while interpolating missing pixels within the deinterlaced image
  • A step of storing interlaced images and intermediate variables in shared memory divided into multiple banks and executing synchronization for all threads within a block
  • Asynchronous data transfer where a second stream performs data transfer between the host and the graphics processing unit while one stream executes kernel operations

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Incheon National University
Jeon Gwang-gil
Document
Date of application:
2015-08-31
|
Patent registration number:
10-1652264
Industry
broadcasting•communication
Technology
Image processing
Computer
Country
Korea
Family Patent

N/A

Price
4000000
Fixed price
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