This technology involves forming a Y2O3-doped alloy thin film by repeating a supercycle that combines TiO2 ALD and Y2O3 ALD processes in a 16:1 ratio, creating a material suitable for quadruple patterning.
Double patterning has reached its limits in semiconductor micropatterning, and SiO2, used for quadruple patterning, fails to meet requirements for thin-film density and etch selectivity. While TiO2 is a promising alternative due to its high density, it suffers from increased surface roughness caused by crystallization during subsequent heat treatment.
This technology suppresses TiO2 crystallization through hetero-element alloying, reducing surface roughness from 1.92Å to 1.53Å even after 400℃ post-deposition annealing. It can be applied to patterning processes for ultra-fine logic devices and high-density memory, reliably supporting linewidth scaling beyond lithography limits.
This invention was developed with support from the Ministry of Trade, Industry and Energy for the development of SiN/SiO2 plasma atomic layer deposition processes and alternative technologies for gate spacers and multi-patterning.
WO2018-139746A1