Device and Method for Reducing Power Consumption in Synchronous Integrated Circuits Utilizing Sparse Activity in Artificial Neural Networks

Low-Power Synchronous Neuromorphic Circuit Device Based on Neuron Sparsity Detection and Clock Gating

This technology is a power-saving device for synchronous integrated circuits that detects sparse activity—where neuron output is zero in an artificial neural network—using logic gates and registers, and employs clock gating to disable the clock for neuromorphic unit cell registers accordingly.

As deep learning workloads have grown, mobile CPUs and FPGA accelerators consuming over 10W have become unsuitable for battery-powered devices like smartphones and wearables. Unlike spike-based asynchronous neuromorphic circuits, digital synchronous circuits suffer from continuous dynamic power consumption by the clock, even when no useful computation is occurring.

This technology uses OR gates and registers to determine n-bit neuron activity, then generates an enable signal via an AND operation with a valid signal to switch the clock of processing elements, preventing unnecessary operation in inactive semi-systolic multiplier unit cells. This enables dynamic power reduction proportional to activity levels even in synchronous circuits. It can be applied to smartphones, wearables, and always-on voice/video recognition chips, extending battery life while enabling continuous on-device AI inference.

‍

‍

Key Features:

• An activity detection unit that senses sparse activity where neuron output in an artificial neural network is zero
• A clock gating circuit unit that blocks the clock input to the clock pin of registers within neuromorphic computing system unit cells based on sparse activity detection
• An OR gate receiving n-bit neuron activity values, a first register feeding back its output, and a first AND gate generating an enable signal by performing an AND operation with a valid signal
• A second register outputting the enable signal based on the clock, and a second AND gate performing an AND operation on that output with the clock, where the processing element is a semi-systolic multiplier unit cell

‍

This invention was developed with support from the Ministry of Education’s research project on general-purpose embedded neuromorphic processors for the Internet of Things.

‍