This technology is a manufacturing method for electrical devices for MOS capacitors. It involves depositing a nitrogen-free, low-chlorine hafnium precursor, Hf(EtCp)2Cl2, onto a silicon substrate via oxygen plasma atomic layer deposition to form an HfO2 dielectric layer, followed by high-temperature annealing and ruthenium electrode sputtering.
As transistor scaling has reduced SiO2 dielectric films to under 2nm, tunneling-induced leakage current has surged, leading to increased power consumption and reduced reliability. The HfCl4 precursor, commonly used for depositing the alternative high-k material HfO2, has high chlorine content, which causes thin-film contamination and degrades electrical properties.
This technology utilizes a low-chlorine precursor to secure HfO2 thin films with reduced chlorine contamination, achieving low leakage current density and stable capacitor performance even after high-temperature processing at 1000°C. Due to the excellent step coverage of atomic layer deposition, it can be uniformly applied to gate oxide films in 3D structures like FinFETs. This technology can be applied to next-generation MOSFET gate dielectrics and memory capacitor manufacturing, providing high-purity high-k insulating films that withstand high-temperature heat treatment in fine-pitch processes, and can be extended to other high-k materials such as ZrO2 and TiO2.
This invention was developed with support from the Ministry of Trade, Industry and Energy for the development of SiN/SiO2 plasma atomic layer deposition processes and alternative technologies for gate spacers and multi-patterning.
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