PACKAGE OF ELECTROMECHANICAL DEVICES AND METHOD THEREOF

CMOS-compatible highly integrated 3D semiconductor device vacuum package

This technology is about electromechanical device packaging technology, and is about an electromechanical device package and method that can implement an electromechanical device package capable of three-dimensional integration with high integration on a semiconductor chip.

Existing electromechanical device packaging suffers from performance degradation due to a reduction in chip area and structural instability problems due to damage to the metal wiring layer. This technology proposes an electromechanical device package capable of high-density three-dimensional integration and a manufacturing method thereof.

The active area is vacuum packaged without affecting the metal wiring layer, maximizes CMOS process compatibility based on TEOS, realizes high integration even with a low metal wiring layer, and can be manufactured at low cost using the existing CMOS process.

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Key Features:

• Forms a fine space (active area) between metal wiring layers for the operation of electromechanical elements through the sacrificial layer deposition and removal process.
• Vacuum sealing with a passivation layer (protective film) and shielding layer ensures structural stability without affecting other metal layers.
• Increases process compatibility based on TEOS (Tetraethyl orthosilicate).
• Affects other metal layers. Implementing a structurally stable CMOS-NEM reconfiguration logic by manufacturing the package only within a specific area

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This technology was developed through the National Research Foundation of Korea's research project on the development of a CMOS-nano-electromechanical hybrid function conversion logic system using monolithic three-dimensional integration technology.

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