A processor capable of handling external service requests using a symmetric interface

Processor architecture technology for processing external service requests with a symmetric interface

This technology concerns a processor capable of handling external service requests through a symmetric interface. More specifically, it is a processor architecture that processes external service requests using a symmetric interface.

Conventional technologies faced the challenge of performance degradation and complexity in multiprocessor systems, necessitating a processor capable of handling external service requests without IRQ pins and interrupt controllers. This technology addresses this by proposing a processor architecture that includes a symmetric interface, a service control point, and an internal buffer for storing and processing service requests.

Accordingly, this technology can improve the efficiency and performance of multiprocessor systems by providing a processor capable of handling external service requests without requiring IRQ pins and interrupt controllers. It has valuable applications in the fields of semiconductors, equipment, electronic components, and software.

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Key Features

• Implements processor architecture technology to handle external service requests via a symmetric interface
• Processes external service requests without interrupts through a symmetric interface and an internal buffer
• Improves the efficiency and performance of multiprocessor systems by providing a processor capable of handling external service requests without requiring IRQ pins and interrupt controllers
• Applicable to the interrupt processing structures of multiprocessor SoCs and embedded processors

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